1. Field of the Invention
The invention relates in general to a method of programming a memory.
2. Description of the Related Art
NAND type memories are widely used in various data storage applications. The NAND type memories may be classified into various types including, for example, a multi-level cell (MLC) NAND type memory. FIG. 1 (Prior Art) is a schematic illustration showing threshold voltage distributions of a multi-level cell NAND type memory. Threshold voltage distributions A to D are usually defined as those sequentially corresponding to 11, 10, 00, 01. Each threshold voltage distribution in FIG. 1 has to be converged so that a sufficient read window may be kept.
The MLC NAND type memory has many multi-level cells. Before the multi-level cells are programmed, threshold voltages of these multi-level cells pertain to the threshold voltage distribution A. When the multi-level cell NAND type memory is being programmed, a threshold voltage of the multi-level cell to be programmed into “10” is programmed from the threshold voltage distribution A to the threshold voltage distribution B. Then, a programming verification process is performed according to a programming verification voltage PV1. Next, the threshold voltage of the multi-level cell to be programmed into “00” is programmed from the threshold voltage distribution A to the threshold voltage distribution C, and then the programming verification process is performed according to a programming verification voltage PV2. Thereafter, the threshold voltage of the multi-level cell to be programmed into “01” is programmed from the threshold voltage distribution A to the threshold voltage distribution D, and then the programming verification process is performed according to a programming verification voltage PV3.
However, during the process of programming the threshold voltage of the multi-level cell from the threshold voltage distribution A into the threshold voltage distribution B, some of the multi-level cells to be programmed into the threshold voltage distribution C may be programmed into the threshold voltage distribution B in advance based on the prior art architecture. However, no programming verification process is performed on these multi-level cells according to the programming verification voltage PV1. Consequently, during the process of programming the threshold voltage of the multi-level cell from the threshold voltage distribution A into the threshold voltage distribution C, the threshold voltages of these multi-level cells are too high so that an error occurs when the multi-level cell is being read according to read voltages RD1/RD2/RD3.
Similarly, similar conditions also occur when the threshold voltage of the multi-level cell is programmed from the threshold voltage distribution A into the threshold voltage distribution C. Some of the multi-level cells to be programmed into the threshold voltage distribution D may be programmed. Thus, it is an important direction to be tried in the industry to correctly program the multi-level cell without generating the too-high threshold voltage.